1. Field of the Invention
The present invention relates to the field of panel displaying techniques, and in particular to a substrate for array process of panel display device, manufacturing method and corresponding liquid crystal display device.
2. The Related Arts
Recently, as the technology develops rapidly, panel displaying techniques, in particular, liquid crystal display (LCD) are widely applied in mobile phone, notebook PC, desktop display device, TV, and so on, and gradually replaces the conventional cathode ray tube (CRT) to become the mainstream display device because of the advantages of high resolution, reduced thickness, light weight, and low power consumption.
The manufacturing process of LCD device usually includes three stages, i.e., the first stage of array process, the second stage of cell process and the third stage of module process. As shown in FIG. 1, in the array process, a plurality of areas 11 corresponding to display panels is formed simultaneously on a glass substrate 10, with each of areas 11 corresponding to display panels electrically connected through a corresponding shorting bar pad set 12 to a corresponding polymer stabilization vertical alignment (PSVA) mode pad set 14 of PSVA mode pad set 13 so as to apply voltage to each display panel during array process to form pretilt angle of liquid crystal molecules. In addition, close to border of glass substrate, 10, PSVA mode pad set 13 further includes a PSVA mode color filter (CF) pad 15, electrically connected to transfer structure 16 on glass substrate 10, wherein transfer structure 16 is used for conducting vertical signals between upper and lower substrates.
Furthermore, also refer to FIG. 2. All scan lines G1, G2, . . . , Gn on each area 11 corresponding to display panel are electrically connected respectively to corresponding scan lead 17, then electrically connected to each corresponding scan pad respectively of shorting bar pad set 12 corresponding area 11, and then electrically connected to scan pad of corresponding PSVA mode pad set 14 of PSVA mode pad set 13. All data lines D1, D2, . . . , Dm on each area 11 corresponding to display panel are electrically connected respectively to corresponding data lead 18, then electrically connected to each corresponding data pad respectively of shorting bar pad set 12 corresponding area 11, and then electrically connected to scan pad of corresponding PSVA mode pad set 14 of PSVA mode pad set 13.
Also, shorting bar pad set 12 corresponding to area 11 further includes common signal pad “corn” and color filter pad “CF”, wherein common signal pad com is electrically connected to common electrode of area 11 and color filter pas CF is connected to transfer structure 16 of area 11 for transferring signals vertically between upper and lower substrates.
Accordingly, PSVA mode pad set 14 of PSVA mode pad set 13 further includes common signal pad “com”, electrically connected to common signal pad com of shorting bar pad set 12.
Therefore, in array process, voltage is applied through pad of corresponding PSVA mode pad set 14 of PSVA mode pad set 13 for pretilt angle processing of liquid crystal molecules of each area 11.
However, as shown in FIG. 1 or 2, when number of areas 11 corresponding to display panels on glass substrate 10 is large, or number of types of signals of short-circuit bar in each area 11 is large, number of pads of PSVA mode display pad set 13 at border of glass substrate 10 is also large, resulting in increase in number of probes for applying voltage during PSVA test. As the number of PSVA test probes increases, probability of bad contact will also increase to cause PSVA curing anomaly, leading to defect rate of display panel. Besides, when number of areas 11 corresponding to display panels on glass substrate 10 is large, or number of types of signals of short-circuit bar in each area 11 is large, the overall design complexity of peripheral routes also increases